1. Field of the Invention
This invention relates generally to error correcting systems and, more particularly, to an on-the-fly error checking and correction (ECC) system for variable block lengths.
2. Description of the Prior Art
The following references disclose basic and significant aspects of prior art error correcting systems:
1. I. S. Reed and G. Solomon, "Polynomial Codes Over Certain Finite Fields", J. Soc. Indust. Appl. Math, 8 (1960) p. 300-304;
2. U.S. Pat. No. 4,494,234 "On-The-Fly Multibyte Error Correcting System" by Arvind M. Patel;
3. U.S. Pat. No. 4,525,838 "Multibyte Error Correcting System Involving a Two-Level Code Structure" by Arvind M. Patel;
4. U.S. Pat. No. 4,706,250 "Method and Apparatus for Correcting Multibyte Errors Having Improved Two-Level Code Structure" by Arvind M. Patel;
5. U.S. Pat. No. 4,907,233 "VLSI Single-Chip (255,223) Reed-Solomon Encoder with Interleaver" by Leslie J. Deutsch et al.;
6. U.S. Pat. No. 4,916,701 "Method and System for Correcting Long Bursts of Consecutive Errors" by John S. Eggenberger et al.; and
7. U.S. Pat. No. 4,951,284 "Method and Means for Correcting Random and Burst Errors" by Khaled Abdel-Ghaffar et al.
Most data storage subsystems associated with modern information handling systems employ some type of error correction system in order to obtain cost effective design for high reliability and data integrity. The ability of the data processing system to retrieve data from the storage system, i.e., access time, is a well recognized measure of the efficiency of the overall storage system. In most data processing systems, the decoding time for the error correction code is a direct factor in the total access time. As the capacity of storage devices has increased, the need for increased reliability and availability has also increased. As a result, the time required to process soft errors by the error correcting system becomes a larger percentage of the total access time.
In direct access storage devices (DASD's), typical ECC schemes implement error correction in such a way that data flow is temporarily interrupted, while microcode routines examine the syndromes or partial syndromes and generate correction vectors. One advantage of a microcode implementation is flexibility. Variable block sizes are accommodated cheaply, and in a straightforward manner. However, typical microcode implementations are not fast enough to prevent additional disk revolutions when reading sequential data.
It is desirable to provide an ECC system that provides single burst on-the-fly correction of variable data block lengths with minimal hardware complexity and cost. It is further desirable to provide an improved ECC decoder that implements a Reed-Solomon (RS) code which can correct one byte per interleave and can detect multiple errors in the interleave.